|本期目录/Table of Contents|

[1]李宁宁,师玲萍.基于时间递归神经网络的轨道车辆自检系统设计[J].工业仪表与自动化装置,2023,(04):58-63.[doi:10.19950/j.cnki.cn61-1121/th.2023.04.011]
 LI Ningning,SHI Lingping.Design of rail vehicle self-test system based on time recursive neural network[J].Industrial Instrumentation & Automation,2023,(04):58-63.[doi:10.19950/j.cnki.cn61-1121/th.2023.04.011]
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基于时间递归神经网络的轨道车辆自检系统设计

《工业仪表与自动化装置》[ISSN:1000-0682/CN:61-1121/TH]

卷:
期数:
2023年04期
页码:
58-63
栏目:
出版日期:
2023-08-15

文章信息/Info

Title:
Design of rail vehicle self-test system based on time recursive neural network
文章编号:
1000-0682(2023)03-0058-06
作者:
李宁宁1师玲萍2
1. 西安交通工程学院 机电学院,陕西 西安 710300;
2. 西安铁路职业技术学院 机电学院,陕西 西安 710026
Author(s):
LI Ningning1 SHI Lingping2
1.School of Mechanical & Electrical Engineering, Xi’an Traffic Engineering Institute, Xi’an 710300, China;
2.School of Mechanical and Electrical Engineering, Xi’an Railway Vocational&Technical Institute, Xi’an 710026, China
关键词:
轨道车辆故障检测神经网络LSTM模型压缩硬件加速FPGA
Keywords:
rail vehiclefault monitoringneural networklong short-term memorymodel compressionhardware accelerationfield programmable gate array
分类号:
TP311.52
DOI:
10.19950/j.cnki.cn61-1121/th.2023.04.011
文献标志码:
A
摘要:
针对轨道车辆内部复杂的信号和多样化的故障类型,为提高故障自检的快速性和有效性,设计了一种基于时间递归神经网络的轨道车辆自检系统,此系统中包含了基于FPGA的神经网络加速器、信号处理芯片、通信模块和传感器。加速器是利用时间递归神经网络LSTM作为自检系统内部智能化神经网络模型,采用剪枝、量化和编码等方式对模型进行了轻量化压缩,最后设计相应的加速器部署在自检系统中,同时完成了LSTM网络轻量化压缩实验和神经网络加速器实验。实验结果表明,自检系统的神经网络压缩算法的设计虽然使模型准确率下降了12.1%,但是压缩率可达7.1%;加速器部分在FPGA部署时仅占用了1.28%的硬件存储资源,性能可以达到200 MHz,吞吐率为19.39 GOPS。
Abstract:
In order to improve the rapidity and effectiveness of fault self-detection, a rail vehicle self-detection system based on time recursive neural network is designed, which includes neural network accelerator, signal processing chip, communication module and sensor based on FPGA. The accelerator uses the time recursive neural network LSTM as the internal intelligent neural network model of the self-checking system. The model is lightweight compressed by means of pruning, quantization and coding. Finally, the corresponding acceleration circuit is designed and deployed on the accelerator, and the LSTM network lightweight compression experiment and neural network accelerator experiment are completed.The experimental results show that although the design of the neural network compression algorithm reduces the model accuracy by 12.1%, the compression rate can reach 7.1%. In FPGA deployment, the accelerator occupies only 1.28% of the hardware storage resources, and the performance can reach 200 MHz with a throughput of 19.39 GOPS.

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备注/Memo

备注/Memo:
收稿日期:2023-04-21

基金项目:
陕西省教育科学“十三五”规划2020年度课题(SGH20Y1631);
西安交通工程学院中青年基金项目(2022KY-35)

第一作者:
李宁宁(1987—),女,甘肃庆阳,本科,讲师。研究方向:轨道车辆结构修造。
更新日期/Last Update: 1900-01-01